What you’ll be doing:

Define/plan/implement/execute verification strategy of complex CPU designs.

Ability to delve into lowest level details of CPU unit design specification, implementation and it's core level impact.

Interactions with design engineers to define detailed verification scope.

Draft detailed verification testplans.

Define/Create a scalable constrained-random verification environment using SystemVerilog and UVM.

Drive stimulus, comprehensive coverage strategy to show continuous progress towards tape-out.

Lookout for continuous improvement of verification flows/processes.

Agility to work on multiple tasks/projects.

What we need to see:

Recently completed a BS or MS in EE/CS or related field (or equivalent experience).

Minimum 6 months experience with CPU verification / validation and software programming.

You have strong programming fundamentals in SystemVerilog/Python/C/C++ and assembly

Understanding of ARM A64, X86 Architectures.